Eric DELAGE
ASIC/FPGA Design Expert
ASIC/FPGA design expert with more than 15 years of experience in all aspects of system-on-chip/-fpga architecture and design. I currently focus on realtime data-streaming computation-intensive applications and rapid platform generation/IP core design reuse methodologies.
I have a passion for all aspects of digital system design. The ambitious projects are specially motivating ; I like working in team to address the challenges posed by the competitors. I work hard to create some opportunities to start my own business in the digital field ; any help would be greatly appreciated.
My technical skills:
# SoC/SoPC architectures for multimedia, communication, networking apps
# Signal processing for digital communication
# Image processing for digital photography
# Processor and memory architectures
# ARM, MIPS, Xilinx processors
# NoC/NoPC endpoints and switches
# Highest density Xilinx FPGAs
# Rapid platform generation
# IP core design reuse
# ASIC, FPGA design flow
My management skills:
# Commitment to insurance quality processes
# ASIC/FPGA project planning & monitoring
# Post-graduate trainee & junior engineer coaching
My language skills:
# French : native
# English : fluent
# German : fluent (daily use)
Several experiences abroad : 3 months in 1996 in Eindhoven (The Netherlands), 18 months in 1999-2000 in Hamburg (Germany), 7 months in 2002-2003 in Freiburg (Germany). These were great opportunities to better understand other cultural environments and to learn from their ways of thinking and working.
My recommendations are on LinkedIn at the address http://fr.linkedin.com/in/ericdelage
79 contactsAs a Member of the Synopsys SNUG San Jose Technical Committee, I review technical publications submitted by authors/speakers attending the SNUG Conferences in the US.
2003 - 2009Development Center of Normandy, France
Telecom Business Unit, Hardware Design Group
# Responsible for the specification, design and verification of multiple system-on-FPGA architectures - targeting the highest density devices of the Xilinx Spartan-3 and Virtex-5 FPGA families - for professional wireless communication receivers and high-performance computer clusters.
# Responsible for the specification, design and verification of multiple system-on-FPGA architectures for data-streaming over 350Mb/s TCP and 950Mb/s UDP networks. Study of architectures supporting data transfers through multiple 1Gb/s Ethernet links simultaneously.
# In-depth study of data-streaming computation-intensive system-on-chip architectures using the concept of network-on-chip with special focus on network switches supporting simultaneously best-effort and guaranteed services.
# Development of several reusable IP libraries including about 80 highly configurable IP cores.
# Setup of a FPGA design methodology focusing on rapid processor-based (IBM/PowerPC or Xilinx/MicroBlaze) platform generation, IP design reuse and efficient HDL verification.
# Coaching of several post-graduate trainees.
2002 - 2003IC Design Center of Freiburg, Germany
Digital Design Group
# Responsible for the design and verification of a 100MHz digital signal processor and its integration in a 400Kgates single-processor system-on-chip for portable audio appliances.
# Participation to several workgroups on the specification of a company-wide IC design process with strong requirement for IP design reuse.
2000 - 2002IC Design Center of Caen, France
Digital Media Business Line, Imaging Group
# Responsible for the specification of an 800Kgates single-processor (ARM946E-S) system-on-chip for digital still-/motion-picture camera (including the choice of its hardware/software partition).
# Responsible for the specification of several DTL-compliant image & video processing cores.
# Contribution to the design and verification of a DTL-compliant JPEG compression core.
# Deployment of PHILIPS/DTL point-to-point protocol and PHILIPS/CoReUse design methodology.
# Coaching of several junior engineers.
1999 - 2000System Laboratory of Hamburg, Germany
Video Compression and Storage Group
# Responsible for the survey of the digital camera market and the specification of a digital still-/motion-picture camera reference appliance.
# Specification of an 800Kgates two-processor (MIPS/R3000 & MIPS/R1900) system-on-chip for digital still-/motion-picture camera (including the choice of its hardware/software partition).
# Performance study of MIPS-based system-on-chips including: C modeling of the underlying hardware system; study of the DIAB compiler, assembler and linker suite; C programming of boot code and benchmarks.
# Coaching of a post-graduate trainee.
1995 - 1998IC Design Center of Caen, France
Digital Media Business Line, Imaging Group
# Responsible for the specification, design and verification of the 250Kgates image and video processing sub-system of a single-processor (MIPS/R3000) system-on-chip for 1.3Mpixel digital still-picture camera.
# Development of several ICs for the Imaging market.
# Coaching of a post-graduate trainee.
Read my recommendations on LinkedIn:
http://fr.linkedin.com/in/ericdelage/fr
