Philip Cacharelis

SiPCUBE designs system-in-package (SiP) products for OEM customers.

Responsibility for establishing strategic alliances and sourcing agreements with SiP technology providers; silicon interposer, embedded die substrate, through silicon via (TSV) and fan-out technologies. Selection and management of packaging and assembly service providers as well as test development partners. Business development activities including technology roadmap definition, competitive analysis, customer identification, business process development, market research, and the strategic positioning of the company.

Responsible for all engineering functions within the organization and comprising four management groups; Customer Engineering, Product/Yield Engineering, Corporate ESD Development and Test Development Engineering. Development of methodologies for the overall business process and budgetary responsibility. Coordination of new process technology development under customer NRE. Task Force leader for the 180 nm Smart Power (HV CMOS & NVM) Joint Development Program with IBM. Member of the Corporate Technical Board (CTO-equivalent entity).

Management of three Process Integration groups with the charters to develop BCD Smart Power, Embedded Non-volatile Memory and Advanced DMOS Device technologies. These groups developed 0.35 to 0.18 um, 25 – 80V BCD Smart Power technology, HiMOS embedded Flash Memory and low cost EEPROM as well as advanced technologies such as deep trench isolation and super-junction DMOS. Responsible for production ramps and yield, technology roadmap definition, business case development and process technology development budgets.

Management of a Liquid-Crystal-on-Silicon (LCOS) microdisplay development team for HDTV applications including responsibility for circuit design, process technology development, microdisplay fabrication, test development, process transfer and production ramp. The process technology was co-developed with an IDM partner and was based on 0.5 um embedded EEPROM technology.

Senior Engineering Manager, Power BiCMOS Technology Development group, Analog Process Technology Development organization.

Management of the process technology development of a 0.72 um Smart Power technology comprising 0.72 um CMOS, embedded non-volatile memory, complementary bipolar, and quasi-vertical and lateral Power DMOS devices. Responsibility for process technology development, power device and memory cell optimization and characterization, and TCAD process simulation.

Senior Engineering Manager, Process Development group, Light Valve Business Unit.

Management of the process technology development for an LCOS microdisplay based on a novel 0.8 um EEPROM technology (developed for embedded NVM products). Optimization of the key optical performance requirements of the process technology for the silicon “light valve” backplane. Process transfer to volume production at Chartered Semiconductor.

Engineering Manager, Embedded Non-volatile and Mixed-Signal Module Development group, Technology Research and Development organization.

Project management for a modular 0.72 um, high performance, double polysilicon EEPROM technology program including process technology development, TCAD process simulation, memory cell design and simulation, circuit design implementation and process transfer.

Engineering Project Manager, Non-volatile Memory Development group

Process Architecture Definition, Development, Device Characterization, Memory Cell Design and Production Site Transfer of a 1.0 um CMOS Double Polysilicon EEPROM technology.

Process Architecture Development and Memory Cell Design and Characterization of a 1.0 um CMOS Single Polysilicon EPROM Programmable Logic Device technology

Principal Engineer, Process Architecture Development and Memory Cell Characterization of a 2.0 um CDMOS Double Polysilicon EEPROM PLA Technology.

Staff Engineer, Process Development for a 2.0 um CMOS/SOS Gate Array technology. High Voltage PMOS technology development and reliability qualification.