Christophe Cortemiglia

Christophe Cortemiglia

System Software and Silicon Validation Engineer

En recherche active
 

En poste chez Intel

Précédents : Samsung Electronics, Texas Instruments, IBM, Thales Avionics (Ex Thomson CSF Detexis), I3S laboratory (Sciences University of Nice)

 

Précédents : Université Nice Sophia Antipolis

 

    En résumé

    • 15+ years of experience driving large scale Low Level SW projects in an international environment • Expert in Validation, Debug , Analysis and Reporting with excellent C coding skills • Linux Kernel development Drivers (USB) • Permanently pushing for efficiency and innovation, successfully deployed novel methodologies • Strong Low Level SW background for the semiconductor industry • Good communication skills and team spirit with ability to work in multi-cultural environments Languages and SW Environments: • C • ARM Assembler (32 and 64 Bits) • System Verilog • Clearcase, ICM • UNIX, LSF • Linux Basic Knowledge, TCL, Perl FPGA Pre-Silicon Prototyping: • Zebu (Synopsys) • HAPS (Synopsys) • Virtual Prototyping (Synopsys) • Veloce (Mentor Graphics) Debug Tools: • Lauterbach • Code Composer Studio Pre-Silicon Tools • NCSIM • Modelsim Laboratory Tools: • Tektronix DPO/TDS Scopes and AWG Data Generator • Agilent MSO Scopes Protocols Analyzers: • USB Lecroy Voyager/Advisor • USB Beagle 5000 • SATA Bus Doctor Multi-Cultural Frame Work • Work with Korean Teams • Work with Chinese Teams • Work with US/India Teams • 2 months in San Diego (CA) • Customers Support

Parcours

 

Pre and Post Silicon Validation Engineer

Chez Intel

De avril 2015 à aujourd'hui
-> Low Level Software and Kernel Drivers Developments for USB Silicon Validation on Modem Platforms -> Validation on Physical Board -> Validation on Pre-Silicon FPGA (Veloce) -> Plan Definition, Reviews and Schedule Definition -> High Cooperation with Chinese, German and US Teams
 

System and Silicon Validation Engineer

Chez Samsung Electronics

De août 2013 à mars 2015
Verification and Validation on Samsung LSI Exynos Products. -> Software Functional Drivers Implementation -> Validation on Board and on FPGA Platforms (HAPS ans ZeBu) -> Plan Definition, Reviews and Schedule Definition -> System Verilog RTL Pre-Silicon Verification -> Expertise on standards ...
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SATA Software Development, Validation and Debug on OMAP5 platform

Chez Texas Instruments

De novembre 2012 à août 2013
-> Software Functional Drivers Implementation -> Validation on Board -> Plan Definition, Reviews and Schedule Definition -> Expertise on standards for SATA (ATA, ATAPI)
 

USB3 and USB2 Software Development, Validation and Debug on OMAP5 and OMAP4 platforms

Chez Texas Instruments

De février 2009 à novembre 2012
-> Software Functional Drivers Implementation -> Validation on Board -> Plan Definition, Reviews and Schedule Definition -> Expertise on standards for USB3.0, Device and Host (xHCI) -> Expertise on standards for USB2.0, OTG1.3, ULPI, UTMI, EHCI, OHCI -> Super Speed Electrical Certification (Eye ...
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Functional Validation on Modem Devices

Chez Texas Instruments

De novembre 2006 à février 2009
Software Functional Drivers, Validation on Board, Plans Definition, reviews and schedule definition for several features like: -> Memory Interfaces (DDR, SDRC, NAND) -> USIM, 3G Topics (Notions of HSPA and WCDMA) -> Power Management -> I2C, SPI, Boot Secure, DMA. -> Tests Automation
 

Design Verification and SW Validation on Modem Devices

Chez Texas Instruments

De juin 2002 à novembre 2006
Design Functional Verification (RTL and GATE Simulations), Validation on Board, Plans Definition, for several features like: -> UART/IrDA and Basic Serial Interfaces -> DSP C64xx
 

Specification Reviewer for OMAP1610 Modules

Chez Texas Instruments

De novembre 2001 à juin 2002
Contractor via STUDIEL Company -> Within the OMAP Architecture Division -> Technical Specifications Reviewer OMAP Modules delivered by Architects like DMA, Memory Interfaces, GPIO …
 

Microelectronic Engineer

Chez IBM

De novembre 2000 à novembre 2001
Contractor via ASTEK Company -> Within the IBM Microelectronic Division -> Design and Verify IPs components for Data Packet Routing (UDASL switch). -> Implement Robustness and Stress Tests -> Put in place Automation and Optimization Tests
 

Software Engineer

Chez Thales Avionics (Ex Thomson CSF Detexis)

De janvier 2000 à novembre 2000
Secure Tests for Military Plane RAFALE F1 for DASSAULT AVIATION -> Within the Avionic Division -> Software Implementation for Display Attack for Aircraft Touch Screen -> Tests Specifications Definition and Validation (“V-Cycle”), -> Real Time Tests on Simulation Platform (Power PC) -> ...
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Engineer School Internship

Chez I3S laboratory (Sciences University of Nice)

De janvier 1999 à juin 1999
Vector Quantization for Satellite Image Processing (Wavelet Transform) -> Collaboration with CNES (Centre National d’Études Spatiales) -> Develop Best Image Compression for the 3S2 satellite -> Compare Study between Scalar Quantization to Vector Quantization.

Langues parlées

 

Centres d'intérêt

 
  • Cooking
  • Tennis