Ludovic MIRANDA

En résumé

Entreprises

• Amesys - Physical implementation engineer

  Aix-en-Provence 2016 - maintenant

• Bull - Internship Engineer

  Les Clayes-sous-Bois 2015 - 2015 Nowadays, frequencies of submicron technology circuit is continuously increasing and it becomes primordial to understand physical phenomenon which were not important on previous technology. Thus, clock jitter needs to be measured and minimized into a complete system (ASIC and boards).
  
  The main principal missions during this internship are:
  – Theory understanding of clock jitter: What are jitter, and its components, as random or deterministic. How to measure it and characterized it in time and frequency domain.
  – Develop a timing jitter budget methodology for a complete system: Jitter from external board due to clock generator quartz. Jitter from internal sources as PLL and clock tree.
  – Theoretical and real jitter measurements in the complete system: With signoff tools as Voltus from Cadence, and PrimeTime from Synopsys, I developed a flow which estimates IR-drop in the design and then determines clock jitter due to this physical phenomenon.
  – Define design rules to limit jitter impacts: As IR-drop is the major contributor, all methodologies which permits to reduce it, will reduce clock jitter.

• Polytech Nice-Sophia - Digital conception project

  2014 - 2015 Design in VHDL under ModelSim environment and Xilinx Vivado of an IP which simulates the Rule-Length-Encoder (RLE) algorithm in order to implement it into a Virtex 5 (Xilinx) System On Programmable Chip (SoPC):
  • 32-bits read/write buffer for configuration
  • 2 512-FIFO buffer (input and output) containing 32-bits words
  • Clock and reset signals
  • Control signals
  
  

• Polytech Nice-Sophia - Graduation project

  2014 - 2014 During this project, I designed an entire system in Cadence Virtuoso environment.
  • Analog part: Theoritical calculation and Spice simulation:
  o Operational Transconductance Amplifer (OTA)
  o Comparator
  o Ramp generator
  • Digital part: Theoritical calculation and Spice simulation:
  o 16-bits counter
  o D Flip-Flops
  Layout: DRC (Design Rule Check) and LVS (Layout Versus Schematic) verification
  

• CRE TECHNOLOGY - Summer intern

  BIOT 2014 - 2014 CRE Technology was developping a new generator controller: GENSYS Compact.In order to ensure it functions properly after production phase, I developped in collaboration with an intern engineer a test bench. I was in charge of the hardware part of the bench. I had to thought about the best system to test all the functionnalities of the Compact. In this way, the bench is able to test all the inputs/outputs of the controller. The inputs (analogs and digitals) are tested by sending to the controller some characteristics signals, and check if it receives them correctly. In the same idea, creating some signals from the controller, and check the values on the output, permits us to test digital outputs. Furthermore, this bench is totally indepedent and communicates through MODBUS TCP/IP with the controller and the PC to display results on tests.
  
  One of the most important part of this bench is to program the microcontroller of the GENSYS with its main software. But the only way is to use the JTAG interface of the controller. So, to simplify this operation, I designed a small USB-JTAG adaptator. I made the layout of the board with DesignSpark, an electronic design software provided by RadioSpares.

• Polytech Nice-Sophia - Digital conception Labs

  2014 - 2014 During these labs, I learnt how to write VHDL code in order to optimize RTL synthesis for implementing on an ALTERA FPGA.
  
  All the Labs are based on the same structure:
  • Simulation and functional validation of the VHDL code - ModelSim (ALTERA)
  • RTL synthesis - Precision Synthesis (MENTOR)
  • Logic optimization - Precision Synthesis (MENTOR)
  • Place and route - Precision Synthesis (MENTOR)
  • Programmation and Circuit test - Quartus II (ALTERA)
  • Post-Layout Simulation - ModelSim (ALTERA)
  
  • LAB1: Seven-Segment display synthesis
  • LAB2: Finite state machine synthesis
  • LAB3: ROM/Macros and counter synthesis
  • LAB4: Partitioned design synthesis

• I3S - Summer intern

  2013 - 2013 At the I3S Laboratory, an aircraft is currently been set up for experimental flights. To this end, a
  series of sensors have to be installed onboard the aircraft. The goals of my project were to equip the aircraft with the following features:
  * Temperature sensors
  * Motor speed sensor
  * Current consumption
  * Data broadcasting
  The main features of this project were the following: Hardware and software design, sensors, interface, C/C++ programming.

• Polytech Nice-Sophia - Digital conception project

  2013 - 2013 Development and simulation of a Von Neumann calculator under ModelSim in VHDL:
  • Memory blocks
  • Datapath
  • Control Unit
  • Top-level architecture
  

• Sophia Team - Secretary

  2012 - 2013 During this project, I was in a team, and we had to design a robot to participate at the cut France of robotics 2013. I was in charge of the secreteriat of the project.
  Concerning the robot himself, I had to implement and code in C a LCD screen to perform the interaction with the robot. Also, I wrote some drivers for the different sensors of the robot.

Formations

• University Of Western Ontario

  London 2013 - 2013 Exchange program in electrical engineering:
  * Advanced Digital Systems
  * Very Large Scale Integration (VLSI)
  * Fundamental of MEMS
  

• Université Nice Sophia Antipolis

  Nice 2009 - 2015 Engineer degree
  
  Engineer cycle specialized in Circuit and System Design.

• LYCEE AUDIBERTI

  Antibes 2006 - 2009 Baccalauréat scientifique
  
  Mention AB