Pascal Aristote
DO-254 IP - Responsable technique, DMAP
DMAP Design Methods and Assurance Process
La solution en IP DO-254 ready
Besoin d’une expertise DO254 ?
Besoin d'une IP DO-254 ready ?
PCI Express, Gigabit Ethernet, CAN, ARINC429,...
Nos actions :
- Mise à niveau d'IP existantes (Reverse engineering)
- Référentiel DO254
- Développement d'IP DO-254 compliant
- Sensibilisation et formation
- Conseil (définition d’une stratégie, accompagnement)
- Expertise (audit des pratiques actuelles, suivi de la migration)
- Outils (aide au choix, attentes, développement spécifique)
- Accompagnement à la certification
Définition d’une stratégie de développement hardware compatible DO254.
Gestion de projet de développement d'IP en DO-254, méthode du reverse engineering.
Développement de référentiel DO-254.
Développement d'IP DO-254 et vérification OVM en SystemVerilog:
- PCI Express Endpoint x1 Gen1 (Verilog)
- Ethernet 1000/100/10Mbits (Verilog)
- CAN (ARINC825) (VHDL)
- ARINC429 (VHDL)
- USART (VHDL)
Projet développement FPGA A350XWB en DO-254 DAL A.
2007 - 2009USB 3.0 IC Project leader.
Leading IP Architecture and USB system development on a xHCI Host Controller IP and USB 3.0 High bandwitdh mass storage Device IP
- Involved in the IPs architecture definition, design and verification.
- Support pre-sales.
- Team & Project management.
Design and Verification Engineer
- DC and Conformal flow expert on PLDA PCIe IPs
- Front End Verification on PCIe Gen 2.0 IPs
2000 - 2007* Design and Verification engineer on a 2.5 and 3G mobile baseband.
- 2 CPU (one dedicated to system control and one for multimedia application)
- 2 DSP for Telecoms protocols and audio processing
- 65nm technology - 49 millions of transistors
Lead the ARM system controller verification.
- integration in the top level chip (IO muxing, gate simulation, timing closure)
- integration of AHB peripherals (UART, SPI, USB,...)
- Top level formal proof (whole chip) with Conformal. RTL to Gate, Gate to Gate.
Lead the definition and integration of a mobile DDR333 controller.
- Validation using ARM C compiler
- IO constraints (placement/timing)
Lead the development of a High Speed NOR memory controller
- Architecture definition (Compatible with main memory maker and technology)
- Synchronous interface up to 104MHz: CellularRAM, OneNAND...
- VHDL development and verification with Specman
- Top level integration and verification with ARM C compiler
- Timing closure after P&R.
* Design and Verification of a 3G-UMTS Companion chip.
- 0.18um - 12 millions of transistors
Responsible of design and verification of UMTS modules
Test patterns creation (IDD Current, process speed, functional test)
- Power analysis with PrimePower tool
* Design and Verification of a low cost 2.5G baseband for mobile application
- 90nm - 12 millions of transistors - ARM 946 CPU.
Integration of a video application engine.
- LCD controller, CAM controller 3M pixels, Video converter.
- 8051 Controller (C and Assembler)