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Pierre BUHAS

GRENOBLE

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Grenoble ainsi que le résultat des européennes dans l'Isère.

En résumé

CV available at http://www.box.net/shared/aj05z2qrj1dmkn3t1sfa


Micro-electronics and ASIC/FPGA Digital Conception:
- HDL design (Verilog and VHDL)
- IPs packaging, Integration and system assembly
- Clocks, reset, power domains managements
- DFT insertion

Application Engineering:
- Pre/post-sales cycles
- Products deployment
- Customers support and training

Informatics:
- Java, C, Jruby, VBA
- Scripting : Ruby,Perl, Tcl, sh
- Linux (Ubuntu, RedHat, Centos)
- VirtualBox
- Web HTML design

Mes compétences :
ASIC
Digital
FPGA
Microelectronics
Soc
VHDL

Entreprises

  • DATA SYSTEMS & SOLUTIONS

    maintenant

  • ST-Ericsson

    maintenant

  • Duolog Technologies - Application Engineer

    2008 - 2009 I am in charge of support, deployment and customization of EDA digital front-end design products
    - Spinner IO Fabric generator [IOMuxing and Chip Top generation]
    - Bitwise Register management [IP HW/SW integration, memory maps, registers]
    - Weaver IPs assembly and connectivity [IP packaging and system assembly]

    ¤ Product deployment and customization in ASIC & FPGA digital conception environment (Verilog, VHDL, SystemV, ...)
    ¤ Customers solutions development for all common design flows including HTML, RTF (Word), FrameMaker, Structured FrameMaker, SystemVerilog (OVM , UVM and VMM), Specman 'e' (VR_AD), ANSI C (API), HDL (Verilog and VHDL), System C (PV - SCML), JTAG BSDL, ...
    ¤ Product enhancements specifications

    ¤ Customers support. Pre-sales and post-sales activities, evaluations and trainings.
    ¤ Training - Customer & Internal teams
    ¤ Support database and tracking system maintenance
    ¤ Demos and showroom management

  • EASII IC - Digital design Consultant at ST Microelectronics

    Grenoble 2007 - 2008 • Responsible for the Chip top level in a wireless mobile platform project
    • Register Transfer Level (RTL) releases for the top level for the ASIC project
    • IO muxing specifications, HDL generation flow upgrades
    • Design flow methodology and EDA tools evaluation:
    Spinner (from DUOLOG, Dublin): pad muxing management
    0-in (Mentor Graphics): Clock Domain Crossing verification

  • DataSystems&Solutions - 3rd year engineering school internship

    2006 - 2006 • Study and conception of a library of arithmetic operators and real data type functions for FPGA
    • Synthesis and Place & Route of test cases on Actel FPGA
    • Study of algorithm accuracy in fixed point or floating point arithmetic for an embedded calculator
    • Development of C test benches to check operators accuracy

  • Flexody - Ingénieur RTL

    2006 - 2007 • RTL for Flexbridge: Co-emulation solution for SoC prototyping systems
    HDL implementation and hardware specifications of the Accellera's Standard Co-Emulation
    Modeling Interface (SCE-MI) standard.
    • Involved in the validation process of the product with the specification and coding of test cases
    for the embedded transaction logic
    • Linked Library development for a Co-simulation solution :
    Architecture and code of the C interface using the Modelsim (Mentor Graphics) Foreign
    Language Interface

  • AuviTran - 2nd year engineering school internship

    2005 - maintenant • Electronic test bench card design to validate a digital audio managing card
    • Development of different test procedures embedded in a Spartan 2E (Xilinx) FPGA
    • Simulation, debug and PCB, Ethersound standard

Formations

Réseau

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