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Thomas TRAVERSIER

SAINT LAURENT DU VAR

En résumé

See my references on Linkedin:
http://www.linkedin.com/in/ttravers

Main skills:
• SoC/IP architecture
• RTL development (design, simulation, synthesis, timing analysis,...)
• Advance verification (SystemVerilog / OVM)
• Team lead

Main hardware knowledge:
• IPs integration & verification
• Hardware implementation (synchronisation mechanism, clock domain crossing, pipelined, clock system, low power design, power management, ...)
• ARM processor architecture
• External memories interfaces (Flash, PSRAM, SDRAM, ...)
• AES cipher/CCM encryption
• Low Energy Bluetooth protocol

Entreprises

  • Accent-SoC - Technical leader / SoC & IP architect

    2010 - maintenant Define architecture of future smart grid chipset and participate to the development:
    - Hardware architecture specification, RTL design, and OVM based verification
    - Custom CPU for low power operations
    - Generic packet handling to be integrated into Modem/Radio for 802.15.4g standard

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    Handle a team of 4 persons in charge of the 180nm ASIC development for smart grid market (SoC with ZigBee radio, metrology, and analog macros):
    - Write all SoC architecture specification, IPs selection, RTL design
    - In charge of the power management unit: design and analogs macro integration
    - Build verification environment for 4-ways cache controller with OVM methodology

    FPGA and testchip samples validation

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    Handle a team of 5 persons in charge of the 65nm ASIC development, for video streaming processing application. Involve in all technical’s parts of the project from front-end to back-end:
    - SoC architecture specification, IPs selection, RTL design, IO ring, floor plan, …
    - Follow and support the SoC development
    - BOM for uSD packaging and BGA packaging

  • Atmel - Design and verification engineer

    Rousset 2010 - 2010 Work in smartcard unit.
    Consolidate design and verification team for new secure chip product:
    - Design security features of new smart card chip
    - Write and update testcases based on AVR assembler
    - Development of functional tests

  • NXP / ST-Ericsson - IP architect and designeer

    2007 - 2009 Work in NXP connectivity/bluetooth department.

    In charge of hardware specification, architecture and design of Low Energy Bluetooth controller, to be integrated into combo FM/GPS/Bluetooth chipset.

    Work in parallel with system architect, firmware team, and verification/validation teams.

    - Control of the radio
    - Data chunk management
    - Bit stream (build packets, CRC, whitening)
    - AES encryption
    - Verification plan
    - Support for firmware/verification/validation teams

    Involve in other design and verification tasks of the combo chipset.

  • Texas Instruments - Electrical Design Engineer

    Villeneuve-Loubet 2004 - 2007 I was a member of the System architecture and verification team. I was in charge of the verification and design of externals memories controller. On top of these main activities, I contributed to critical debug of several tricky issues.

  • Esterel technologie - Verification Engineer

    2002 - 2004 I worked as sub-contractor for Texas Intruments. I integrated the EBU (Ericsson Business Unit) as a verification engineer.

Formations

Réseau

Pas de contact professionnel

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