Wireless ASIC , Front-End Experience: - VHDL / Verilog RTL design - DFT / BIST / ATPG - RTL simulations - Synthesis / STA - Formal Verification - Gate Level simulations.

Working in a team for library qualification and process calibration of the 65nm and 45nm technologies. Responsible for the functional validation ,STA and test patterns generation for silicon validatio ...

International Team Lead & Project Management - Multi-cultural context (US, Europe, India) - Organize tasks and plannings, priorities, dependencies - Identify blocking situations and coordinate actions - ...

Project: Ensure the quality of Hardware/Software releases - Design blocks: VHDL, Verilog, System Verilog - Test bench creation: VHDL, Verilog, System Verilog, C++ - Automatic check: script, Makefile - ...