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Laurent LEFEBURE

Velizy Villacoublay

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à la Celle-Saint-Cloud ainsi que le résultat des européennes dans les Yvelines.

En résumé

Customer project manager with good communication skills and pro-active team player.
Working in competitive market industry and enjoy customer interactions.
Quick and innovative to find solutions.

Specialties:
* Team coordination (US, India, Poland, France)
* Project management in international environnement (US, Poland, India, China, Russia, Norway, England, Italy, Israel, Tunisia)
* IP delivery and quality accountable
* Customer services for digital ASIC development (technology down to 16nm, 3D TSV, FDSOI)

Mes compétences :
Microélectronique
GDS
Cadence
Tcl
EDI
Synthesis
Asic
DDR

Entreprises

  • Cadence Design Systems - IP project manager

    Velizy Villacoublay 2013 - maintenant IP Project Manager and delivery worldwide (US, France, China, India ) for semiconductor companies such as ST Microelectronics, ARM, Cisco, Sony, Ceragon, Parrot, …
    - Scoping definition (planning and resource need)
    - Driving weekly follow up with customer
    - Accountable for the quality and the deliverables.
    Type of IP : LPDDR / DDR3 / DDR4 / HSIC PHY
    http://www.cadence.com

  • Cadence Design Systems - Services project manager

    Velizy Villacoublay 2010 - 2013 Services project management for semiconductor companies across Europe (NXP, ST Microelectronics, Advantest, Thalès, Parrot, Coppergate, …), also involved in european funded project (Catrene 3DIM3) in following areas:
    - Scoping definition (task, planning and resource needs)
    - Technical follow up with customer
    http://www.cadence.com

  • Cadence Design Systems - Lead Application Engeneer

    Velizy Villacoublay 2004 - 2013 Services delivery in France and Europe for large semiconductor companies (NXP, ST Microelectronics) and fabless companies (Thalès, Parrot, Semtech, Thomson…), mainly in two areas:
    - ASIC physical design (Examples: design RTL-to-GDSII of consumer device 90nm ; synthesis, place and route for a large, hierarchical System-On-Chip 0.180um to 65nm)
    - Design flow definition and implementation for deep submicron designs (Signal integrity, physical synthesis,…). On-the-job training for the customer’s designers.
    http://www.cadence.com/

  • Alpi - Programmer

    COLOMBES 2002 - 2004 ALPI is editor of caculation and schematics softwares for electrical installations. Its products have been designed for engineering departments and electrical contractors within the service and manufacturing industries.
    http://www.alpi.fr/

  • ST Microelectronics - Digital ASIC Backend flow support

    2001 - 2002 -CAD Support: validation and technical support of a physical implementation and verification flow (RTL to Layout) for a 64bits microprocessor.
    -ASIC hierarchical physical implementation: top-down physical implementation of the 64bits microprocessor

Formations

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