Peter Nowottnick

Peter Nowottnick

Senior IC Architect, Digital Design at IC'ALPS

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En poste chez IC'Alps

Précédents : CXignited, TAGSYS RFID, ELO Touch Solutions, Tyco Electronics / Sensitive Object, DxO Labs, MND (Methodologies & Designs), On Chip Solutions (OCS), T.Sqware / GlobeSpan / GlobespanVirata, T.Sqware / Globespan, T.Sqware, Universität der Bundeswehr Hamburg, Technische Universität Braunschweig, IBM Deutschland

 

Précédents : Helmut-Schmidt-Universität, Helmut-Schmidt-Universität Universität Der Bundeswehr Hamburg, Technische Universität Braunschweig, Technische Universität Carolo-Wilhelmina Zu Braunschweig / TU Braunschweig

Parcours

 

Senior IC Architect, Digital Design

Chez IC'Alps

De janvier 2019 à aujourd'hui
Responsible for the specification of the IC / SoC devices and/or blocks constituting it (features, performance, verification methods by simulation and on silicon), in relationship with customers, project managers, and other designers. Vis-à-vis customers, being the technical guarantor of the ...
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Product Development Manager

Chez CXignited

De décembre 2016 à mars 2018
Responsible for the development and delivery of a RFID-based infrastructure for Real-Time Inventory and Localization (RTIL) Systems. - Lead actively the definition and implementation of the RTIL software platform as well as the infrastructure hardware and its interfaces to the system software ...
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Product Development Manager

Chez TAGSYS RFID

De novembre 2014 à novembre 2016
Responsible for the development and delivery of a RFID-based infrastructure for Real-Time Inventory (RTI) Systems. - Lead actively the definition and implementation of the RTI software platform as well as the infrastructure hardware and its interfaces to the standard software products. - ...
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Principal R&D Engineer

Chez ELO Touch Solutions

De septembre 2012 à juillet 2014
* Strong interaction between physics design team and platform implementation team. Performed all stages of embedded system development from conceptual design and architecture definition down to hardware and software implementation. * Provided solutions for embedded systems ...
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Embedded DSP Expert

Chez Tyco Electronics / Sensitive Object

De septembre 2010 à septembre 2012
* Provided DSP and microprocessor expertise for touch solutions using APR (Acoustic Pulse Recognition) system "ReverSys" * Specification, follow-up and maintenance of APR front-end firmware implementation on Audio-DSP device. * Interaction with design team of back-end processor system (embedded ...
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VLSI Development Manager

Chez DxO Labs

De janvier 2007 à août 2010
* Management of VLSI/RTL design and verification group (4 engineers) * Architecture definition of microprocessor systems dedicated to high performance digital image processing (ISP, Digital Optics) * Designed and implemented RTL modules of the IPC microprocessor core and assured their ...
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Hardware Technical Leader / Co-founder

Chez MND (Methodologies & Designs)

De avril 2004 à décembre 2006
en-Yvelines, France ``VLSI Technical Leader'' * Technical leadership for RTL and software design group (5 engineers) * System architecture definition with focus on hardware/software partition * Designed and implemented RTL modules (e.g. DDR Controller, coprocessor / ...
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Hardware Project Leader / Microprocessor Expert

Chez On Chip Solutions (OCS)

De février 2003 à mars 2004
Preparation of company startup ``OCS'', Saint Quentin-en-Yvelines, France * ``Microprocessor Expert'', focused on reconfigurability aspects of the system architecture and future extensions * Specified and implemented a MMU for the SPARClet architecture
 

Network Processor Expert

Chez T.Sqware / GlobeSpan / GlobespanVirata

De octobre 2002 à janvier 2003
* Investigated SoC solutions using the SPARClet processor * Technical expert for knowledge transfer to U.S. based LSI design group (training and support)
 

Validation Team Leader

Chez T.Sqware / GlobeSpan / GlobespanVirata

De avril 2000 à janvier 2003
 

Technical Leader & Validation Team Manager

Chez T.Sqware / GlobeSpan / GlobespanVirata

De janvier 2001 à septembre 2002
``Validation Technical Leader'' and ``Validation Team Manager'': * Provided Technical Leadership to the 9 engineers of the telecom product validation group * Definition and implementation of automatic test environment used for the entire system validation system (device under test, ...
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Conformance and System Test Senior Engineer

Chez T.Sqware / Globespan

De février 2000 à décembre 2000
* Product validation of HDLC processing software/firmware from concept through specification, implementation, and execution of tests * Implemented and extended automatic test execution for non-regression tests * Prepared the process and product for a successful conformance tests for ...
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Application Group Leader

Chez T.Sqware

De mars 1998 à janvier 2000
* Led 3 engineers working on functional hardware validation * Specified test and evaluation boards; Technically responsible for subcontractors * Provided customer support and was technical contact for US customers and link between worldwide FAEs and the Application Lab in France ...
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Member of Architecture Simulation Group

Chez T.Sqware

De septembre 1997 à février 1998
* Extended and maintained the SPARClet Architecture Simulator ``SASlet'' ; * Ported application software to run on the simulator
 

Helmut-Schmidt-Universität, Hamburg

Dr. Ing., Helmut-Schmidt-Universität

De septembre 1992 à août 1997
Technische Informatik - Work in european research project SMILE (Sparc Macrocell Interface and Library Elements), part of ESPRIT program. Specialized on Microprocessor Architecture Simulation.
 

Helmut-Schmidt-Universität Universität Der Bundeswehr Hamburg, Hamburg

Doctor of Philosophy, Helmut-Schmidt-Universität Universität Der Bundeswehr Hamburg

De mai 1992 à août 1997
``Dr.-Ing.'' (Ph.D.) in Electrical Engineering, '' Dissertation: ``A tool to support the performance evaluation of real-time computing systems'' * Embedded Microprocessor Architecture Simulation and associated Tools
 

Research Assistant

Chez Universität der Bundeswehr Hamburg

De 1992 à 1997
* Delivered to a European research project (SMILE, part of ESPRIT/OMI): 1) Clock-tick precise, timing accurate C-module of the SPARC-CPU for the architectural simulator 2) Specification and implementation of the performance analysis tool ``ASAP'' * Doctoral Thesis - Research in ...
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Research Assistant

Chez Technische Universität Braunschweig

De 1991 à 1992
* Development and improvement of a new design principle of fault tolerant integrated circuits with low overhead, called FBR (functional block redundancy). Co-holder of a patent (DE 40 38 610 C 1)
 

Intern

Chez IBM Deutschland

De 1984 à 1990
2 periods (3 months): Full custom chip design and test (macro-cell design)

Compétences

 
  • Architecture systèmes embarqués
  • C Programming Language
  • C++
  • Customer support
  • DSP
  • Electrical Engineering
  • embedded firmware implementation
  • Full custom chip design
  • Voir toutes les compétences (21)

Langues parlées

 

Centres d'intérêt

 
  • aviron
  • bricolage
  • chant
  • photographie