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Pierre-Yves CHALLIER

MILANO

En résumé

Pas de description

Entreprises

  • PHILIPS Semiconductors

    maintenant
  • Cadence Design Systems - Field Application Engineer

    Velizy Villacoublay 2008 - maintenant EDA company (5200 empl in world) location: Lund (swedeen, 5 years) Agrate ( Italy: 1 year)
    Pre-post-sale activity , business development and reporting .
    • Support Conformal suite tools for Customer in different European location
    o deeply involve on project
    design automation, bug report and follow-up, tapeout .
    o pre-sale activity
    new product presentation and advertising
    customers successes stories
    Training given

    • Support ETS, TEMPUS; STA (several european location )
    o pre-sale activity
    o onsite support and debug
    o reporting and customer meeting management

  • Dolphin integration - Senior Design Engineer

    Meylan 2006 - 2007 Microelectronics, IP , electronics and services company (150 empl in world)
    • Texas Instruments subcontractor:
    o Image processor project: Equivalence checking ( lec, Cadence ), RTL verification , Power estimation, power isolation verification .
    o For front end camera module: Power isolation verification, power rule check (spyglass ).
  • MOSYS - Field Application Engineer

    2005 - 2006 Memory IP provider. (100 empl world-wide, 2 empl in Europe, HQ in California USA)

    • Evangelize and promote 1T-SRAM to new markets.
    o Prospect and win targeted customers by adopting MoSys technology to the customer’s application.
    o Covering all Europe, including Israel .
    o Propose new architectures and new market segments to the US management team.

    • Work closely with IDMs (Intel, Atmel, Philips, ST) and foundries (TSMC , SMIC, UMC, Chartered, a.o.).
    o Create and release customer datasheets.
    o Reporting to US management team (customer requirements, competition, new opportunities).

    • Representing MoSys at the Same Conference technical and start-up committee in Sophia-Antipolis.
    • Organized Mosys’ participation to conferences (IP SOC - Grenoble, Same conference – Sophia-Antipolis).
  • Thales Microelectronics, TES - Sub contractor for Texas Instrument and Atmel

    2004 - 2005 Microelectronics, electronics, SSII and boards services company (800 empl in Europe)
    • Texas Instruments (4 months ):
    o Synthesis and static timing analyses.
    • Atmel Subcontractor, SAM7 Product line (6 months):
    o Integrated IP block and validated final design.
  • Tachys technologies - Digital Project Leader

    2001 - 2003 Start-up on high speed links, IP provider (30 empl in Europe)

    • Strip library, Chinon (chip): Standard and Mixed library for serial transmission 0.13m TSMC
    • Architect and Design Infiniband repeater 1x.
    o VHDL coding. Bloc synthesis 360 MHz with Ambit.

    • Participate to the Chinon test chip architecture definition.
    o Complexity around 150 kgates with a full custom and analog component integrated.
    o Integrated Infiniband 1x repeater, XGMII, PCI express 4x.
    o Assisted on the co-simulation (VHDL / C++ ) installation (Testbuilder Cadence).

    • Broadway-Pegasus project: serial link 3.125 Gbit/s, 0.18m TSMC
    • Project leader, digital portion: project planning, reporting, and management
    o Back-end interface (subcontracted to Cadence).
    o Help on synthesis flow 360 MHz Ambit.

    • Architect and Design the FPGA (Altera) which allows chip test and an easy to use software interface.
  • VLSI technology - Design Engineer

    1996 - 2001 ASIC provider and foundry, bought by Philips Semiconductor. (1500 to 20000 empl)

    • OakDSPcore 1996-2001
    • Core improvement and technology porting (4 technologies : 0.35, 0.25, 0.20, 0.18 m)
    o Design improvement: speed, design modifications, synthesis.
    o Complete test flow: Sunrise, Tetramax.
    o Static Timing Analysis: Critical path, input output characteristic (quad motive, primetime).

    • Arm703T, Arm940T test chip 1997-1998
    o Adapted production vector (delivered by Arm ltd).
    o Bonding diagram and interface with the product engineer.
    o Technologic migration, speed improvement, STA.

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