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Thomas MALLARD

Colombelles

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Toulouse ainsi que le résultat des européennes en Haute-Garonne.

En résumé

I am IC analog/mixed signal designer. I am particularly interested by data-converters, high speed data transmission and power management.

Mes compétences :
Microélectronique
Electronique analogique
CMOS
VHDL
Spectre Software
Microsoft Office
Matlab
HSPICE
Virtuoso Software
Verilog
Transistors
Tcl/Tk
Python Programming
PLL
Microelectronics
Java
Cadence Software
C Programming Language
Analogue Design

Entreprises

  • NXP Semiconductors - Analog IC designer

    Colombelles 2015 - maintenant

  • FREESCALE - Analog IC designer

    Toulouse 2015 - 2015

  • Xilinx - Analog IC designer

    San Jose 2013 - 2015 SerDes team (Gigabit transmitters, high speed I/O).

    Responsibilities: design/verification of analog blocks in CMOS 28nm, 20nm (planar
    Mosfet) and 16nm (Finfet). Full design of OTA and bias circuits. Some work
    involved in clocking and front-end blocks.

    Design with Cadence Virtuoso, simulation with HSPICE, Spectre and BDA. Using
    of scripts languages like Python or Skill/Ocean.
    One paper published
    3 patents approved by all the levels of the company, pending at the US patent office
    Supervision of a 4th year bachelor academic project at the University College of
    Cork: design of a DCO for all-digital PLL.

  • Infineon Technologies - Intern

    GEMENOS 2013 - 2013 Topic: Design-for-test/Built-in-self-test: design of a very pure signal generation based on sigma-delta modulation: SFDR of 100dB reached with a chip area of 49x49 μm2 (chip manufactured).
    Tools: Design with Matlab, VHDL, Cadence Virtuoso and using of the Technologies C11 (CMOS 130 nm) and C40 (CMOS 40 nm).
    Reference: Jaafar Mejri, principal analog designer at Infineon Technologies, Jaafar.Mejri@infineon.com.

  • NXP Semiconductors - Academic project

    Colombelles 2012 - 2013 Topic: Design and modeling of boost converters; design of a dedicated control system at transistor level.
    Tools: Design with Cadence Virtuoso and using Qubic4Plus BiCMOS 0.25μm technology.
    Reference: Melaine Philip, analog designer at NXP Semiconductors, melaine.philip@nxp.com.

  • University of Guelph (Ontario, Canada) - Intern

    2012 - 2012 Topic: Design and optimization of charge pumps and their control system in order to increase energy efficiency.
    Tools: Design with Cadence Virtuoso and using TSMC CMOS 0.18μm technology.
    Papers: 2 papers published
    Reference: Stefano Gregori, associate professor at the University of Guelph,
    sgregori@uoguelph.ca.

Formations

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