Remy Sartor

EMEA account manager for security products.

It was a Cooperative Education in Engineering School. 3 days a week at school, 3 days a week at work.
Development in VHDL for FPGA chip on Telecom Board control her clock.

It was a Cooperative Education at the University. 2 weeks at school, 2 weeks at work.
Physical Design on a DCDC demo board using Allegro and Concept from Cadence Corp. High voltage and current constraints
Physical Design on a UDASL link board. Dual Speed linked bus constraints to manage.