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Scalinx
- Digital IC Architect
Technique | Paris (75000)
2020 - maintenant
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IC'Alps
- Senior IC Architect, Digital Design
Meylan
2019 - 2019
Responsible for the specification of the IC / SoC devices and/or blocks constituting it
(features, performance, verification methods by simulation and on silicon), in relationship with customers, project managers, and other designers.
Vis-à-vis customers, being the technical guarantor of the performance of the circuit in accordance with the specifications.
Vis-à-vis the team, participating in the debates on architectural choices for research compromise and in the interest of continuous improvement of the design methods.
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CXignited
- Product Development Manager
2016 - 2018
Responsible for the development and delivery of a RFID-based infrastructure for Real-Time Inventory and Localization (RTIL) Systems.
- Lead actively the definition and implementation of the RTIL software platform as well as the infrastructure hardware and its interfaces to the system software product ShopCX.
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TAGSYS RFID
- Product Development Manager
2014 - 2016
Responsible for the development and delivery of a RFID-based infrastructure for Real-Time Inventory (RTI) Systems.
- Lead actively the definition and implementation of the RTI software platform as well as the infrastructure hardware and its interfaces to the standard software products.
- Participate in architecture definition of the stardard software platform FiTS.
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ELO Touch Solutions
- Principal R&D Engineer
2012 - 2014
* Strong interaction between physics design team and platform implementation team.
Performed all stages of embedded system development from conceptual design and
architecture definition down to hardware and software implementation.
* Provided solutions for embedded systems architecture (hardware and software) and
design methodology for APR-based touch sub-systems
* Specified and implemented the APR front-end firmware in the dedicated embedded
Audio-DSP device
* Provided support and co-developped firmware in stack-machine based dedicated
touch controller for capacitive touch technology.
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Tyco Electronics / Sensitive Object
- Embedded DSP Expert
2010 - 2012
* Provided DSP and microprocessor expertise for touch solutions using APR (Acoustic
Pulse Recognition) system "ReverSys"
* Specification, follow-up and maintenance of APR front-end firmware implementation
on Audio-DSP device.
* Interaction with design team of back-end processor system (embedded Linux-based)
and physical design team.
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DxO Labs
- VLSI Development Manager
Boulogne
2007 - 2010
* Management of VLSI/RTL design and verification group (4 engineers)
* Architecture definition of microprocessor systems dedicated to high performance
digital image processing (ISP, Digital Optics)
* Designed and implemented RTL modules of the IPC microprocessor core and
assured their verification, including firmware support
* Provided automatic IPC system configuration tool to support marketing and sales
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MND (Methodologies & Designs)
- Hardware Technical Leader / Co-founder
2004 - 2006
en-Yvelines, France
``VLSI Technical Leader''
* Technical leadership for RTL and software design group (5 engineers)
* System architecture definition with focus on hardware/software partition
* Designed and implemented RTL modules (e.g. DDR Controller, coprocessor / specific
instruction set for video codec implementations)
* Provided customer support (via phone and on-site)
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On Chip Solutions (OCS)
- Hardware Project Leader / Microprocessor Expert
2003 - 2004
Preparation of company startup ``OCS'', Saint Quentin-en-Yvelines, France
* ``Microprocessor Expert'', focused on reconfigurability aspects of the system
architecture and future extensions
* Specified and implemented a MMU for the SPARClet architecture
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T.Sqware / GlobeSpan / GlobespanVirata
- Network Processor Expert
2002 - 2003
* Investigated SoC solutions using the SPARClet processor
* Technical expert for knowledge transfer to U.S. based LSI design group (training and
support)
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T.Sqware / GlobeSpan / GlobespanVirata
- Technical Leader & Validation Team Manager
2001 - 2002
``Validation Technical Leader'' and ``Validation Team Manager'':
* Provided Technical Leadership to the 9 engineers of the telecom product validation
group
* Definition and implementation of automatic test environment used for the entire
system validation system (device under test, test boards, and software)
* Planned and tracked the activities of 11 validation engineers on multiple projects
* Developed and delivered project documentation (``Data Book'' etc.)
* Trained software teams locally (in France) and remotely (in the U.S. and India) on
hardware and software aspects of the multiprocessor system
* Resolved implementation problems on 3 platforms: HDLC Controller systems, ATMbased DSL channel aggregation processor, MxU Reference Design
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T.Sqware / GlobeSpan / GlobespanVirata
- Validation Team Leader
2000 - 2003
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T.Sqware / Globespan
- Conformance and System Test Senior Engineer
2000 - 2000
* Product validation of HDLC processing software/firmware from concept through
specification, implementation, and execution of tests
* Implemented and extended automatic test execution for non-regression tests
* Prepared the process and product for a successful conformance tests for a PDH
framer
* Accelerated the learning curve, improved the quality and performance of the software
development team and established a second product validation environment during a
temporary assignment to the U.S.
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T.Sqware
- Application Group Leader
1998 - 2000
* Led 3 engineers working on functional hardware validation
* Specified test and evaluation boards; Technically responsible for subcontractors
* Provided customer support and was technical contact for US customers and link
between worldwide FAEs and the Application Lab in France
* Acted as Product Manager for 672 channel HDLC Controller from firmware
development through end customer product deployment
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T.Sqware
- Member of Architecture Simulation Group
1997 - 1998
* Extended and maintained the SPARClet Architecture Simulator ``SASlet'' ;
* Ported application software to run on the simulator
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Universität der Bundeswehr Hamburg
- Research Assistant
1992 - 1997
* Delivered to a European research project (SMILE, part of ESPRIT/OMI):
1) Clock-tick precise, timing accurate C-module of the SPARC-CPU for the
architectural simulator
2) Specification and implementation of the performance analysis tool ``ASAP''
* Doctoral Thesis - Research in performance evaluation of real-time computing systems
and conceptual work on methods of describing and evaluating performance metrics
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Technische Universität Braunschweig
- Research Assistant
1991 - 1992
* Development and improvement of a new design principle of fault tolerant integrated
circuits with low overhead, called FBR (functional block redundancy).
Co-holder of a patent (DE 40 38 610 C 1)
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IBM Deutschland
- Intern
Bois-Colombes
1984 - 1990
2 periods (3 months): Full custom chip design and test (macro-cell design)
