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Stéphane LABERT

Meudon la Forêt

En résumé

Mes compétences :
VHDL
ARM
SystemC
Verilog
SystemVerilog

Entreprises

  • Mentor Graphics - Customer Application Engineer

    Meudon la Forêt 2001 - maintenant support engineer for different products : HW/SW co-verification, DFT, digital simulation, high-level synthesis
    trainer, presentation of the new functionalities to customers
    Verification Methodology
  • IKOS Systems - Field Application Engineer

    1998 - 2001 Field Application Engineer
    - Pre/post sale support of all Software and Hardware products of the company
    - Demos during shows / evaluation on the customer site
    - Technical presentations to customers
    - Partnership between the sales and the engineering to provide high customer satisfaction
    - C++/SystemC programming
  • LSI Logic - ASIC development engineer

    Ariana 1996 - 1998 ASIC development engineer
    - Perfecting knowledge in VHDL and Verilog.
    - Design of various modules integrated in ASIC (applications MPEG2, ATM)
    - Integration of a RISC processor and its cache memory in a SOC
    - Validation of complete circuits at RTL and gate level.
    - Global synthesis of several circuits
    - Static Timing Analysis of several circuits
  • Philips (LEP) - Design Engineer

    1995 - 1995 Design of blocs used in an ASIC dedicated to video (MPEG2)
    - Behavioral VHDL of each module (CCIR656 decoder, microprocessor interface, FIFO controller between two clock domains)
    - Development of the test environment (testbench)
    - Implementation of the RTL code and functional verification

Formations

Pas de formation renseignée

Réseau

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