David NGUYEN VAN MAU

En résumé

Entreprises

• TiEmpo - Software Architect

  maintenant Technical leader for the back-end synthesis implementation. In charge of implementing the following topics in the asynchronous design compiler:
  
  - Netlist object model
  - Asynchronous Static Timing Analyzer
  - SDC generation
  - TCL interface
  - Logic optimization
  - Asynchronous mapping
  - Asynchronous timing estimation using third-party tools

• Xilinx (Grenoble) - Staff Engineer

  1999 - 2008 Optimizations logique pour outil de synthèse sur technology FPGA:
  
  - macro inference/pattern matching
  - macro-génération
  - glue-logique optimization
  * Minimization
  * Kernel extraction
  * BDD decomposition
  - mapping to netlist.
  - netlist timing optimisation / netlist area optimization
  - physical synthésis
  
  Patents:
  
  - Resource and context based multiplier generation
  http://www.freepatentsonline.com/7627458.html
  - Method and apparatus for improving multiplexer implementation on integrated circuits
  http://www.freepatentsonline.com/7506278.html
  - Method and apparatus for mapping flip-flop logic onto shift register logic
  http://www.freepatentsonline.com/7735045.html

Formations

• Ensimag

  Saint Martin D'Hères 1996 - 1999 Recherche Opérationnelle
  
  RO

Réseau

• Bogdan PAVKOVIC

• Charles GUILLEMET

• Christophe SCARABELLO

• Estelle DEUSE

• N'gaye TRAORE

• Pascale DENIS-OGIER

• Pierre KIEFFER

• Sophie PASQUIER

• Thomas VUILLERMET