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Flavien DELAUCHE

GRENOBLE

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Grenoble ainsi que le résultat des européennes dans l'Isère.

En résumé

Titulaire d’un diplôme d’ingénieur en microélectronique, j’ai poursuivi ma formation avec une thèse sur l'optimisation statistique du rendement paramétrique des microsystèmes (MEMS).
Après 14 ans passés dans la R&D high-tech, je me suis investi 3 ans dans le développement d'une petite société spécialisée dans le domaine de la pulvérisation : standardisation/normalisation, marketing, e-développement, R&D, service client.
Riche de cette nouvelle expérience professionnelle, je travaille aujourd'hui à nouveau dans la microélectronique pour Globalfoundries, qui a repris les usines d'AMD et racheté IBM Semiconducteur.

Mes compétences :
Microélectronique
CAO
PDK
LVS
Support client
DRC
Shell
SVRF
TCL
Perl
TVF
UNIX
Mentor Graphics
data management
Tiling
Tcl/Tk
Semiconductors
Perl Programming
densities management
configuration
company support
Web Responsive Design
Software implementation
Search Engine Optimisation
Linux
Integrated Circuit
EDA tool development
Cadence Software
CAD support and development
CAD support

Entreprises

  • Globalfoundries - RF PDK Design Denablement

    2017 - maintenant

  • Prestaset - Ingénieur Freelance

    2016 - 2017 Senior Physical Verification Engineer (PDK/Design Enablement - DRC, LVS, dummy fill, CAD)

  • Vich - R&D, Marketing, Sales, Purchases

    2013 - 2016 * Vich - R&D, Purchases, Marketing, Sales (sprayer manufacturer, Aubenas, France)
    Normalization/modernization of existing sprayers, R&D and design of new ones
    Creation of a commercial website (vich.fr), Search Engine Optimization, Web Responsive Design, IT

  • STMicroelectronics - Physical Verification Engineer

    2009 - 2013 DRC for ST/ISDA/IBM Alliance cmos technologies down to 28 FDSOI, DRMs review
    Smart tiling (dummy fill/tiles, BE/FE/E-Metrology structures) for the Alliance down to 14 FDSOI
    IP filling methodology and development of a cost-effective approach with Mentor Graphics for post tape-out metal fix/ECO with DesignRev, by modifying a minimum number of masks despite via-tiling

  • ST Ericsson - CAD Support Engineer

    GRENOBLE 2008 - 2009 CAD support, scripting (bash, Perl, Tcl), internal bug tracking system setting
    Support to designers for multi-site projects settings (Unix environment and data management)

  • ARM - CAD Support Engineer

    2007 - 2008 * ARM - CAD Support to Memories team - contractor (
    Memories design flow enhancement, projects configuration and data management
    Member of the task force (multisite) aiming at standardizing design environment, and clarifying processes
    and responsibilities. Interface between memories designers and software developers ,

  • FREESCALE - Physical Verification Engineer

    Toulouse 2004 - 2007 * Freescale (Crolles2 Alliance) - Process Design Kit
    In charge of DRC for cmos 90/65/45nm used by ST, NXP and FSL in CR 12' fab, multi-company support
    Intensive use of Calibre (SVRF/TVF), collaboration with CAD vendors for software optimization
    Work in close collaboration with Design Rule Manuals owners. Quality: 6 sigma green belt training/project ,

  • STMicroelectronics - Physical Verification Engineer

    2003 - 2004 Improvement of development methods and qualification for Design Kits, documentation
    Unix environment setting for Physical Verification team
    Development of DRC/LVS SVRF modules (Physical Verification) down to 130 nm

  • MEMSCAP - EDA PhD student

    1999 - 2003 Statistical optimization of parametric yield for MEMS/ICs through Design Of Experiments (Taguchi)
    Software implementation of the developed algorithm in JAVA language, design of MEMs test structures

Formations

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