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Guillaume PLASSAN

Rungis Complexe

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Grenoble ainsi que le résultat des européennes dans l'Isère.

En résumé

Ph.D with double expertise in microelectronics and computer science.
Experience in ASIC design (VHDL, Verilog, CDC), software engineering (C++, algorithms, data structures) and EDA (static analysis, formal methods).

Highly motivated when facing a good challenge, I love using knowledge from different fields in order to achieve both performance and usability.

Mes compétences :
Microelectronics
VHDL
Python Programming
ModelSim
LaTeX
FPGA
C Programming Language
ASIC
Git
Verilog
CPU Architecture
Clock Domain Crossing
Front-end Design
C++
Algorithms
Formal methods
Spyglass
Perforce

Entreprises

  • Synopsys - Senior R&D Engineer

    Rungis Complexe 2017 - maintenant - Developping multiple linting rules to statically analyze RTL designs (C++, UPF)
    - Customer support on advanced features (formal clock-domain crossing verification)
    - Leading a collaboration with an external research institute

  • Université Grenoble Alpes - Teacher (part-time)

    2015 - maintenant Teaching at Master level:
    VHDL - ASIC & FPGA design flow (RTL, synthesis, STA, P&R, ...) - Functional verification (Simulation/Formal)

  • Synopsys - R&D Engineer

    Rungis Complexe 2015 - 2017 - Research & development of new algorithms for CDC static analysis and formal verification (C++)
    - Customer interaction & support (hardware RTL design)

  • Atrenta - Member of Technical Staff

    2014 - 2015 - Developing new methodologies improving the Spyglass formal verification flow (C++)
    - Collaboration with TIMA Laboratory and STMicroelectronics

  • Stmicroelectronics - CDC Hardware Designer

    2014 - 2014 - Clock Domain Crossing Checks for RTL/Gate-level (VHDL/Verilog)
    ...with statis-analysis tool: Atrenta Spyglass
    ...on CPU subsystems based on multi-core ARM A53/A57

  • Laboratoire TIMA - Research Assistant

    Lyon 2013 - 2013 - Comparative study of specification synthesizing tools
    - Development of an interpreter PSL-DOT-VHDL
    - Experimentation of PSL/LTL specifications on formal-proof related tools

  • EASii IC - Production & Test Intern

    Grenoble 2012 - 2012 - Production test of analog IC, analysis of results and documentation of test procedure
    - VBA development automating the reporting of LabView measurements

Formations

  • Université Grenoble Alpes

    Grenoble 2014 - 2017 Ph.D.

    Thesis: "Conclusive Formal Verification of Clock Domain Crossing Properties"
    How to tackle the infamous state-space explosion on CDC designs while using SAT-based model checking of SVA properties?

  • Grenoble INP Phelma

    Grenoble 2011 - 2014 Engineering Diploma

    CPU Architecture, VLSI, low-power, VHDL, HLS, CAN/CNA, OS & protocols, transistor level, quantum physics, ...
    Projects: Z-buffer algorithm on FPGA, assembly-to-binary in C, MJPEG decoder optimisation on multicore CPU, analog&digital low-band filter with ping-pong buffers

  • Lycée Michel Montaigne

    Bordeaux 2009 - 2011 Classe Préparatoire aux Grandes Ecoles

  • Lycée Fernand Daguin

    Merignac 2006 - 2009 Baccalauréat

Réseau

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