Vélizy-Villacoublay2004 - 20102008-2010 - 24 mois
ST Microelectronics - Grenoble (38)
Standard Linear IC’s Division
Silicon proven IP's Layout of an Audio Amplificator Class G Flipchip product in 0.25um (HF7) technology
Silicon proven IP's Layout of a RF product in 0.13um (H9A) : LDO, XO, IO ring
Silicon proven Top Layout of a FlipChip space product (SerDes from 6.25Gbps to 25Gbps, LVDS RadHard IO) in 65nm technologies
Place and Route of digital blocks
Virtuoso-XL, Calibre DRC LVS, Soc Encounter
2006-2008 - 20 mois
SOFRADIR - Veurey-Voroize (38)
Silicon proven Top Layout and Simulations of InfraRed Imagers in AMI 0.5 and 0.35um technologies
Pixel, Columns Amplis, Bias, Logic, Output Ampli.
Floorplan, Layout Top, Post Layout Simulations
2006 - 3 mois
E2V Semiconductors - St Egreve (38)
Physical Design
IP's Layout of a 12 bits 250MHz ADC in Bicmos 0.18um JAZZ technology
2005-2006 - 15 mois
ST / Philips / Freescale - Crolles 2 Alliance (38)
Design Services - TILT
Test structure development (Reliability, Modeling, Process Development, SRAM, RF structures) in advanced technologies (90nm, 65nm, 45nm and SOI)
2004 - 6 mois
ST Microelectronics - Crolles (38)
Design Kit
DRC validation flow automation in 0.25 and 0.13um (H7A and H9A) technologies
