Menu

Marcello MAGNA DETTO CALCATERRA

MASSY

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Massy ainsi que le résultat des européennes en Seine-Maritime.

En résumé

Mes compétences :
VHDL
Ethernet
SDH
WDM
Verilog
1588v2
ModelSim

Entreprises

  • Alcatel Submarine Networks - FPGA engineer

    2014 - maintenant

  • Alcatel Lucent Italia - FPGA system and architecture engineer - project management

    2009 - 2014 Management of development of projects, for Alcatel-Lucent Italia, Optics Division, based in Vimercate (Italy).
    Management of an internally developed project (FPGAs for a cost reduction of an existing board for Ethernet over SDH STM16), and of a project externally developed by a third company (FPGA which implements a part of the IEEE 1588v2 recommendation, on technology Xilinx Virtex6). In the fist case, the activity consists in being the interface of the development group towards the other entities (Hardware group, Product Manager, Project Leader). In the second case, the activity consists in the preparation of the specification of the FPGA, the following of the development with a nearly everyday exchange with the developers, the supervision of the testing activity in the site of Alcatel-Lucent.
    From 4/2011 I was project leader of a small development team for an FPGA, with direct involvement in the design. Definition of the needs at the system level, discussing them with the System team and the Hardware team; choice of the device (Xilinx Virtex6), definition of the interfaces, setup of the environment for the place&route. Top-level design with integration of the parts developed by the other team members.
    From 2009 to 2011 I was also the reference person for tracking the information and code exchange with the Alcatel-Lucent development group based in China.

  • Alcatel Lucent France - FPGA/system designer

    Paris 2006 - 2009 In the framework of an expatriate contract, the coordination of the development of a transponder card transponder WDM at 10 Gb/s, which concentrates clients either SDH (STM16), WDM (OTU1) and data packet (Gigabit Ethernet) towards the line WDM OTU2: definition of the functionality of the card at a system and equipment level; interface with the team, based in Vimercate in Italy, that develops the FPGA chipset used on the card; development of the FPGA in charge of the control of the card; writing of the hardware/software interface of the card; definition of the algorithms of software management to be coded by the software team.

  • Alcatel Lucent Italia - Digital IC designer

    2000 - 2006 Digital Integrated Circuits (ASIC and FPGA) designer for synchronous optical transport networks (SDH) equipments. I worked mainly on FPGAs, Xilinx and Altera. My main subject of competence is the Virtual Concatenation in SDH (as described in ITU-T G.783).

Formations

  • Politecnico Di MILANO (Milano)

    Milano 1992 - 1999 Ingegneria Elettronica

    Sono stato tutor delle matricole nel 1996/97, studente Erasmus all'ESIEE di Parigi nel 1997/98.

Réseau

Annuaire des membres :